1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device including PMOS transistors and NMOS transistors, and a manufacturing method of the same.
2. Description of the Related Art
It is indispensable in designing an LSI (Large-Scaled Integrated Semiconductor Device) to use a computer for the sake of reduction in time for designing and confirmation and to eliminate man-caused mistakes. A semiconductor device design supporting system using the computer in this manner is referred to as a CAD (Computer Aided Design) system. According to a LSI designing method of cell base, cells of a plurality of types are configured as a library. A designer executes designing of LSI by utilizing CAD and allocating a desired cell in a layout space defined on the computer.
FIG. 1 shows basic cells (primitive cells) for designing a conventional semiconductor device. In each of the basic cells, a power supply line 102 for supplying a power supply voltage VDD and a ground line 103 for supplying a ground voltage GND are arranged along a X-direction. The power supply line 102 and the ground line 103 are connected to a N-type diffusion layer 104 and P-type diffusion layer 105 for applying substrate voltages via contacts, respectively. Further, PMOS transistors P1 to P4 and NMOS transistors N1 to N4 are formed in a region between by the power supply line 102 and the ground line 103. Specifically, a gate electrode 110 is formed along a Y-direction. P-type diffusion layers 112 are formed in a region for the PMOS transistors to be formed to put the gate electrode 110 therebetween, and N-type diffusion layers 113 are formed in a region for the NMOS transistors to be formed to put the gate electrode 110 therebetween. Further, for the sake of isolation or separation of elements, a STI (Shallow Trench Isolation) structure 120 is formed as an element isolation structure.
In a semiconductor device field, in many cases, a plurality of transistors are used collectively. For this reason, each of the basic cells is formed in such a manner that a “transistor group” composed of a plurality of transistors is surrounded by a STI structure 120. For example, in FIG. 1, the PMOS transistor group P1 and P2 is surrounded by the STI structure 120, and the PMOS transistor group P3 and P4 is surrounded by the STI structure 120. That is, the PMOS transistor group P1 and P2 and the PMOS transistor group P3 and P4 are isolated or separated by the STI structures 120. Further, an NMOS transistor group N1 and N2 is surrounded by the STI structure 120 and an NMOS transistor group N3 and N4 is surrounded by the STI structure 120. That is, the NMOS transistor group N1 and N2 and the NMOS transistor group N3 and N4 are isolated by the STI structures 120. Meanwhile, the length of one transistor group in the X-direction is referred to as a “diffusion layer length DL”. In other words, the diffusion layer length DL can be defined as the length between STI structures 120 in the X-direction.
In conjunction with the above description, a semiconductor device is disclosed in Japanese Laid open Patent Publication (JP-P2003-203989A). In this conventional example, the semiconductor device includes P-channel field effect transistors connected in a lattice form. In the semiconductor device of this type, a long active region extending over a plurality of transistors is divided for every gate electrode such that a compression stress is applied to a channel portion of the P-channel field effect transistor. A sufficiently thin STI structure is arranged between the gate electrodes.
Also, a semiconductor integrated circuit device is disclosed in Japanese Laid Open Patent Publication (JP-P2001-345430A), in which element structure MISFET and element isolation MISFET are formed on a main surface of a semiconductor substrate. The element structure MISFET and the element isolation MISFET of include a source and a drain which are formed in a semiconductor substrate, a gate insulating film formed between the source and the drain on the semiconductor substrate, and a doped gate electrode formed on the gate insulating film. Besides, a difference in work function between the gate electrode of the element isolation MISFET and the main surface of the semiconductor substrate is greater than a difference in work function between the gate electrode of the element constitution MISFET and the main surface of the semiconductor substrate.
A stress generated due to isolation of elements by the STI structure (hereinafter, to be also referred to as a STI structure stress) changes the crystal structure. The change in the crystal structure has an influence upon characteristics of transistors, for example, driving capability of a transistor. In recent years, miniaturization of the element has made remarkable progress, and the STI structure stress has become a significant problem. Namely, as the element is miniaturized, the STI structure stress that influences the driving capability of the transistor has become one of factors which cannot be ignored. For example, it is known that magnitude of ON current Ion of the transistor (drain current) fluctuates depending on change in the STI structure stress. Since the STI structure stress depends upon the above diffusion layer length DL as a distance between STI structures, the diffusion layer length DL has an effect upon magnitude of ON current Ion.
FIG. 2 shows dependence of ON current Ion on the diffusion layer length DL. A vertical axis represents ON current IonN of the NMOS transistor and ON current IonP of the PMOS transistor. A horizontal axis represents the diffusion layer length DL. As shown in FIG. 2, in the PMOS transistor, when the diffusion layer length DL is shorter, the ON current IonP is larger. Contrary, in the NMOS transistor, when the diffusion layer length DL is longer, the ON current IonN is larger. In other words, the characteristics of the PMOS transistors can be improved with the shorter diffusion layer length DL and the characteristics of the NMOS transistors can be improved with the longer diffusion layer length DL.
In consideration of miniaturization of the elements, it is desired to provide a technique that can improve the characteristics of ON current (drain current) as much as possible for both the PMOS transistors and the NMOS transistors. When the diffusion layer length DL is simply elongated in the NMOS transistor, many NMOS transistors are arranged in a region between the STI structures. In this case, it is not possible to use a desired number of NMOS transistors among many NMOS transistors. In other words, if the diffusion layer length DL is simply elongated, isolation of a desired number of elements is not possible and handling of a desired number of elements is not possible accordingly.